Polling Eeciently on Stock Hardware

Two strategies for supporting asynchronous interrupts are: the use of the processor's hardware interrupt system and the use of polling. The advantages of polling include: portabil-ity, simplicity, and low cost for handling interrupts. Unfortunately , polling has an overhead for the explicit interrupt checks inserted in the code. This paper describes balanced polling, a method for placing the interrupt checks which has a low overhead and also guarantees an upper bound on interrupt latency. This method has been used by Gambit (an optimizing native code compiler for Scheme) to support a number of features including multiprocessing and stack overrow detection. The overhead of balanced polling is less than for call-return polling which places interrupt checks at every procedure entry and exit. The overhead of call-return polling is typically 70% larger (but sometimes over 400% larger) than the overhead of balanced polling. 1 Introduction In this paper, the term interrupt is deened as an exceptional event for which some special processing is needed (e.g. a heap overrow). The handling of an interrupt is done in three phases. The interrupt is raised when the event occurs. At some point after this the processor detects the interrupt and then handles it by invoking the appropriate interrupt handler. There are two types of interrupts. Synchronous interrupts can only be raised at well deened locations in the code (e.g. an arithmetic overrow or invalid pointer derefer-ence). Asynchronous interrupts can be raised at any location (e.g. a timer or user interrupt).